In recent years, many microprocessors have been improved in processing performance by installing an instruction cache memory or data cache memory. The circuit sizes and power consumption of such microprocessors are restricted. Due to the restriction, in many cases, a complicated configuration or complicated control is not adopted for a cache memory of a microprocessor to improve the performance of the cache memory. Instead, in many cases, a circuit for controlling the cache memory is simplified by employing a direct mapping or a 2-way set associative mapping as a scheme associating blocks of a main memory with blocks of the cache memory.
Further, in recent years, multiprocessor systems have been widely used. Such a multiprocessor system need to have a function to keep coherency among cache memories of processors constituting the multiprocessor. The function may be provided by installing hardware in the multiprocessor system. However, the configuration or control of the hardware may be complicated.
In stead of installing such hardware, the coherency of the cache memories can be kept by a computer program which is executed in the multiprocessor system. However, by providing such a function in the computer program, possibility of generation of bugs may increase.
When debugging such a computer program, data stored in a cache memory needs to be analyzed.
As described above, generation of bugs may increase in a computer program for executing a multiprocessor system, by providing a function in the computer program to keep coherency among cache memories of the multiprocessor system. Thus, a debugging function, which may attain easy analysis, is required.
A debugger capable of displaying data stored in a cache memory of a microprocessor is disclosed in “Online User's Manual for SuperH™ RISC engine simulator/debugger,” issued on Jul. 25, 2007 by Renesas Technology Corp., and searched on the Internet on Sep. 19, 2007 (URL: http://documentation.renesas.com/jpn/products/tool/rjj10b0218_sh.pdf, pp. 97 to 102).
The debugger that is shown in the above document stores data together with tag address information in the cache memory.
The tag address information and the data stored in the cache memory are displayed in an order of index addresses of the cache memory. Thus, it is difficult to know the relation between the data stored in the cache memory and a main memory address, for example.